1. Field of the Invention
The present invention generally relates to a frequency synthesizer, a frequency prescaler thereof, and a frequency synthesizing method thereof, and more particularly, to a frequency synthesizer with low circuit complexity, low power consumption, and broad bandwidth, a frequency prescaler thereof, and a frequency synthesizing method thereof.
2. Description of Related Art
A frequency synthesizer is a device for outputting signals of different frequencies, and is usually applied in the tuner of a broadband communication receiver. When the communication receiver needs to generate signals of different frequencies, the frequency synthesizer provides a high-frequency signal S1 and several signals S2˜SK of lower frequencies, wherein the frequency of the signal S1 is multiples of the frequencies of the signals S2˜SK.
FIG. 1 is a system block diagram of a conventional frequency synthesizer 10. Referring to FIG. 1, the conventional frequency synthesizer 10 includes at least two voltage-controlled oscillators (VCOs) 101 and 102, selectors 103 and 106, a divide-by-3.5 circuit 104, divide-by-2 circuits 105, 107, and 109, and an orthogonal signal separator 108.
The VCOs 101 and 102 are two different VCOs. The VCOs 101 and 102 receive an input voltage Vin and output signals of different frequencies according to the input voltage Vin. The selector 103 is coupled to the VCOs 101 and 102, and selects an output signal of the VCOs 101 and 102 as its output signal. Through the operations of the VCOs 101 and 102 and the selector 103, the selector 103 can output a signal having frequency between 1.8 GHz and 3.3 GHz.
The divide-by-3.5 circuit 104 is coupled to the selector 103 for dividing the frequency of the output signal of the selector 103 by 3.5. The divide-by-2 circuit 105 is coupled to the divide-by-3.5 circuit 104 for dividing the frequency of the output signal of the divide-by-3.5 circuit 104 by 2. Through the operations of the divide-by-2 circuit 105 and the divide-by-3.5 circuit 104, the frequency of the output signal of the selector 103 can be divided by 7.
The selector 106 is coupled to the divide-by-2 circuit 105, the divide-by-3.5 circuit 104, and the selector 103. The selector 106 selects one of the output signals of the divide-by-2 circuit 105, the divide-by-3.5 circuit 104, and the selector 103 as its output signal. In other words, the selector 106 can choose to divide the frequency of the output signal of the selector 103 by 7, 3.5, or to directly output the output signal of the selector 103.
The divide-by-2 circuit 107 is coupled to the selector 106 for dividing the frequency of the output signal of the selector 106 by 2. The orthogonal signal separator 108 generates an orthogonal signal corresponding to the output signal of the divide-by-2 circuit 107 and outputs the output signal of the divide-by-2 circuit 107 and the corresponding orthogonal signal. The divide-by-2 circuit 109 is coupled to the orthogonal signal separator 108 for dividing the frequency of the output signal of the orthogonal signal separator 108 by 2, so as to output two signals Vout_I and Vout_Q, wherein the output signals Vout_I and Vout_Q have the same frequency but the phases thereof have a difference of 90°, and the frequency of the output signals Vout_I and Vout_Q is between 90 MHz and 770 MHz.
The conventional frequency synthesizer 10 requires at least two VCOs 101 and 102, and the VCOs 101 and 102 have larger chip sizes than other components. Accordingly, the chip size of the conventional frequency synthesizer 10 is too large to meet the current trend in the design of electronic products. Besides, the large chip size of the conventional frequency synthesizer 10 makes it very difficult to reduce the fabricating cost.
FIG. 2 is a system block diagram of another conventional frequency synthesizer 20. Referring to FIG. 2, the conventional frequency synthesizer 20 includes a VCO 201, a frequency prescaler 202, a duty cycle corrector (DCC) 203, a multiply-by-2 circuit 204, a frequency divider 205, and a divide-by-2 circuit 206.
The VCO 201 receives an input voltage Vin and generates an output signal having frequency between 7.1 GHz and 8 GHz according to the input voltage Vin. The frequency prescaler 202 is coupled to the VCO 201 for dividing the frequency of the output signal of the VCO 201 by 8 to 15. The DCC 203 is coupled to the frequency prescaler 202 for correcting the output signal of the frequency prescaler 202. The multiply-by-2 circuit 204 is coupled to the DCC 203 for multiplying the frequency of the output signal of the DCC 203 by 2. Through the operations of the DCC 203 and the multiply-by-2 circuit 204, the corrected output signal can have a 50% duty cycle.
The frequency divider 205 is a power-of-2 frequency divider. The frequency divider 205 is coupled to the multiply-by-2 circuit 204 for dividing the frequency of the output signal of the multiply-by-2 circuit 204 by 1, 2, 4, 8, or 16. The divide-by-2 circuit 206 is coupled to the frequency divider 205 for dividing the frequency of the output signal of the frequency divider 205 by 2, so as to generate an output signal Vout.
Since the conventional frequency synthesizer 20 adopts only one VCO 201, the chip size thereof is smaller than that of the conventional frequency synthesizer 10. However, since only one VCO 201 is adopted for achieving the desired frequency range, the frequency of the output signal of the VCO 201 is between 7.1 GHz and 8 GHz. The higher the frequency of the output signal of the VCO 201 is, the more power is consumed by the VCO 201 and the higher circuit complexity the VCO 201 has.
The multiply-by-2 circuit 204 and the DCC 203 have to be disposed in the conventional frequency synthesizer 20 in order to allow the output signal of the frequency synthesizer 20 to have a 50% duty cycle. However, the adoption of the multiply-by-2 circuit 204 and the DCC 203 increases the complexity of the conventional frequency synthesizer 20. Because the frequency prescaler 202 cannot operate with a high-frequency VCO, the frequency of the output signal of the VCO 201 is usually reduced by half. Then the desired frequency of the output signal is obtained through the multiply-by-2 circuit 204. Besides, the frequency divider 205 usually has four divide-by-2 circuits in order to obtain different frequencies. As a result, including the divide-by-2 circuit 206, the frequency synthesizer 20 requires totally five divide-by-2 circuits.